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Wireless Components
ASK Single Conversion Receiver TDA 5200 Version 2.7
Specification March 2000
Revision History Current Version: 2.7 as of 07.03.2000 Previous Version: 2.6, November 1999 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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Edition 03.00 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG March 2000. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TDA 5200
Product Info
Product Info
General Description The IC is a very low power consumption single chip ASK Single Conversion Receiver for the frequency bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life. Package
Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -107dBm
Remote Control Systems
Ordering Information
Type TDA 5200 available on tape and reel Ordering Code Q67037-A1049 Package P-TSSOP-28-1
Wireless Components
Product Info

Application
Keyless Entry Systems

Features
Low supply current (Is = 4.8mA typ. at 868MHz, Is = 4.6mA typ. at 434MHz)
Selectable frequency ranges 868-870 MHz and 433-435 MHz Limiter with RSSI generation, operating at 10.7MHz Selectable reference frequency 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
Alarm Systems Low Bitrate Communication Systems
Specification, March 2000
1
2.1 2.2 2.3 2.4
Table of Contents
i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-2 2-2 2-2 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 3-2 3-3 3-9 3-10 3-10 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 4-2
4.2 4.3 4.4 4.5
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 4-5 4-6 4-7
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 5-2 5-2 5-3 5-4 5-9 5-10 5-12
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5200
Product Description
2.1 Overview
The IC is a very low power consumption single chip ASK Single Conversion Receiver for the frequency bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
Keyless Entry Systems Remote Control Systems Alarm Systems Low Bitrate Communication Systems
2.3 Features
Wireless Components

Low supply current (Is = 4.8 mA typ. at 868MHz, 4.6mA typ. at 434MHz) Supply voltage range 5V 10% Power down mode with very low supply current (100nA max.) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -107dBm Selectable frequency ranges 868-870 MHz and 433-435 MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
2-2
Specification, March 2000
TDA 5200
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2-3
Specification, March 2000
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
TDA 5200
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI M IX AGND FSEL IF O DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP L IM X L IM CSEL LF
TDA 5200
22 21 20 19 18 17 16 15
Pin_Configuration.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Specification, March 2000
TDA 5200
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4 .1 5 V
1
50uA
2 3
VCC LNI
5V Supply LNA Input
57uA
3
500uA 4k
1k
Wireless Components
3-3
Specification, March 2000
TDA 5200
Functional Description
4
TAGC
4.3 V
AGC Time Constant Control
3 uA 4
1k
1 .4u A
1 .7V
5 6
AGND LNO
5V
Analogue Ground Return LNA Output
1k
6
7 8
VCC MI
1 .7 V
5V Supply Mixer Input
2k
2k
9
MIX
8 9
Complementary Mixer Input
4 0 0u A
10
AGND
Analogue Ground Return
Wireless Components
3-4
Specification, March 2000
TDA 5200
Functional Description
11
FSEL
869/434 MHz Operating Frequency Selector
7 50 1 .2 V
2k 11
12
IFO
10.7 MHz IF Mixer Output
300uA
2 .2 V
60 12
4 .5 k
13 14 15
DGND VDD LF
5V 4.6 V
Digital Ground Return 5V Supply (PLL Counter Circuitry) PLL Filter Access Point
30 uA 2 00 15 1 00
30u A
2.4 V
Wireless Components
3-5
Specification, March 2000
TDA 5200
Functional Description
16
CSEL
6.xx or 13.xx MHz Quartz Selector
1 .2 V
8 0k 16
17
LIM
2 .4 V
Limiter Input
15k 17
Complementary Limiter Input
18
LIMX
75uA
330
18
15k
19
SLP
Data Slicer Positive Input
15 uA
100 19
3k
40 uA
Wireless Components
3-6
Specification, March 2000
TDA 5200
Functional Description
20
SLN
Data Slicer Negative Input
5uA
1 0k 20
21
OPP
OpAmp Noninverting Input
5u A
200 21
22
FFB
Data Filter Feedback Pin
5 uA
1 00k 22
23
THRES
AGC Threshold Input
5u A
10 k 23
24
3VOUT
24
3V Reference Output
3V
Wireless Components
3-7
Specification, March 2000
TDA 5200
Functional Description
25
DATA
Data Output
200 25 80k
26
PDO
Peak Detector Output
200 26
27
PDWN
27
Power Down Input
220k
220k
28
CRST2
External Crystal Connector 2
4 .1 5 V
28
50uA
Wireless Components
3-8
Specification, March 2000
TDA 5200
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
LNO 6 RF 3
MI 8
MIX IFO 9 12
LIM 17
LIMX 18
FFB 22
OPP 21
SLP 19
SLN 20 25 DATA
LNA
RSSI
SLICER
TAGC 4
26 23
PDO THRES 3VOUT
TDA 5200
VDD 14 : 1/2 DGND 13 Loop Filter VCO : 128/64 DET Crystal OSC
AGC Reference
24
UREF
Bandgap Reference
2/7 VCC
5/10 AGND
11 FSEL
15 LF
16 CSEL
1
28
27 PDWN
Crystal
Function_5200.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3-9
Specification, March 2000
TDA 5200
Functional Description
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3.2dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 433-435MHz/868-870MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order to suppress RF signals to appear at the IF output ( IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 =to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. It's nominal centre frequency is 852MHz. No additional components are necessary. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. In case of operation in the 433 - 435 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled by the selection pin FSEL (Pin 11) as described in the following table. The overall divi-
Wireless Components
3 - 10
Specification, March 2000
TDA 5200
Functional Description
sion ratio of the divider chain can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below). The loop filter is also realised fully on-chip.
Table 3-2 FSEL pin operating states FSEL Open Shorted to ground RF Frequency 433 - 435 MHz 868 - 870 MHz
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 13MHz range as the overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-3 CSEL pin operating states CSEL Open Shorted to ground Crystal Frequency 6.xx MHz 13.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80dB that has a bandpass-characteristic centred around 10.7MHz. It has an input impedance of 330 =to allow for easy interfacing to a 10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4-2. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to turn down the LNA gain by approximately 17dB in case the input signal strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k=on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
Wireless Components
3 - 11
Specification, March 2000
TDA 5200
Functional Description
3.4.7
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of approximately 120kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for the detector. The self-adjusting threshold on pin 20 its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.8
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The output can be used as an indicator for the signal strength and also as a reference for the data slicer. The maximum output current is 500A.
3.4.9
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA. .
Table 3-4 PDWN pin operating states PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
Wireless Components
3 - 12
Specification, March 2000
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
TDA 5200
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R4
R5
Uthreshold Pins: 24 23 RSSI (0.8 - 2.8V)
+3V
OTA
VCC
Iload RSSI > Uthreshold: Iload=4.2A RSSI < Uthreshold: Iload= -1.5A 4 UC C Gain control voltage
LNA
Uc:< 2.6V : Gain high Uc:> 2.6V : Gain low Ucmax= VCC - 0.7V Ucmin = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage.
Wireless Components
4-2
Specification, March 2000
TDA 5200
Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1
LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50A, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. R4 can be chosen as 120k, R5 as 180k to yield an overall 3VOUT output current of 10A. Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation a voltage lower than 0.7V shall be applied to the THRES, such as a short to ground. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.
Wireless Components
4-3
Specification, March 2000
TDA 5200
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)
(2)
2Q b C1 = ---------------------R2f 3dB
with
b C2 = -------------------------4QRf 3dB
b Q = -----a
where in case of a Bessel filter and thus
(3)
the quality factor of the poles
a = 1.3617, b = 0.618 Q = 0.577
and in case of a Butterworth filter and thus
a = 1.141, b = 1 Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF 1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, March 2000
TDA 5200
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5200 Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1 1 + 2 f X L Cl
with Cl the load capacitance (refer to the quartz crystal specification). Examples: 6.7 MHz: CL = 12 pF XL=750 XL=1250 CS = 8.7 pF CS = 5.3 pF
13.401 MHz: CL = 12 pF
These values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 20pF and 15pF in the 6.7MHz case and 15pF and 8.2pF in the 13.401MHz case.
Wireless Components
4-5
Specification, March 2000
TDA 5200
Applications
4.4 Quartz Frequency Calculation
The quartz frequency is calculated by using the following formula:
QU = (RF 10.7) / r with RF LO QU r .... .... .... ....
(1),
receive frequency local oscillator (PLL) frequency (RF 10.7) quartz oscillator frequency ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table.
Table 4-1 PLL Division Ratio Dependence on States of FSEL and CSEL FSEL CSEL Ratio r = (fLO/fQU) 64 32 128 64
open open GND GND
open GND open GND
Subtraction of 10.7 occurs in case the receive frequency is higher than the intended local oscillator frequency, addition in case the receive frequency lies below the local oscillator frequency. Examples:
f QU = (868.4MHz - 10.7 MHz ) / 64 = 13.40156 MHz
f QU = (868.4 MHz - 10.7 MHz ) / 128 = 6.7008 MHz f QU = (434.2 MHz - 10.7 MHz ) / 32 = 13.23437 MHz
Wireless Components
4-6
Specification, March 2000
TDA 5200
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated using an external R-C integrator as shown in the following . The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20k.
R C
Pins:
19
20 Uthreshold
data out 25
data filter data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
R C R data out 25 Uthreshold
Pins: peak detector
26
19
20
data slicer
data filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4-7
Specification, March 2000
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
TDA 5200
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins Vs Tj Ts RthJA VESD -1 -0.3 -40 -40 max 5.5 +150 +125 114 +1 V C C K/W kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
Wireless Components
5-2
Specification, March 2000
TDA 5200
Reference
5.1.2
Operating Range
Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C # Parameter Symbol Limit Values min 1 Supply Current IS 868 IS 434 RFin -107 max 5.6 5.4 -13 mA mA dBm fRF = 868MHz fRF = 434MHz Unit Test Conditions L Item
2
Receiver Input Level
3 4 5 6 7 8 9
LNI Input Frequency MI/X Input Frequency 3dB IF Frequency Range Powerdown Mode On Powerdown Mode Off Gain Control Voltage, LNA high gain state Gain Control Voltage, LNA low gain state
fRF fMI fIF -3dB PWDNON PWDNOFF VTHRES VTHRES
433/ 868 433/ 868 5 0 2 2.8 0
435/ 870 435/ 870 23 0.8 VS VS 0.7V
MHz MHz MHz V V V V
This value is guaranteed by design.
Wireless Components
5-3
Specification, March 2000
@ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
TDA 5200
Reference
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. The device performance parameters marked with were measured on an Infineon evaluation board as desdribed in Section 5.2..
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V # Parameter Symbol min Supply Supply Current 1 2 3 Supply current, standby mode Supply current, device operating at 868MHz Supply current, device operating at 434 MHz IS PDWN IS 868 IS 434 50 4.8 4.6 70 5.2 5 nA mA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) tied to GND Pin 11 (FSEL) open Limit Values typ max Unit Test Conditions L Item
LNA Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode 1
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode
Wireless Components
5-4
Specification, March 2000
3
Output impedance, fRF=434 MHz
S22 LNA
0.886 / -12.9 deg
2
Gain fRF=869 MHz
S21 LNA
1.419 / 101.7 deg
1
Gain fRF=434 MHz
S21 LNA
1.509 / 138.2 deg
7
LO signal feedthrough at antenna port
LOLNI
-73
dBm
6
Input 3rd order intercept point fRF=869 MHz
IIP3LNA
-14
dBm
matched input
5
Input 3rd order intercept point fRF=434 MHz
IIP3LNA
-10
dBm
matched input
4
Input level @ 1dB compression
P1dBLNA
-15
dBm
3
Input impedance, fRF=869 MHz
S11 LNA
0.738 / -73.5 deg
2
Input impedance, fRF=434 MHz
S11 LNA
0.873 / -34.7 deg
Average Power Level at BER = 2E-3 (Sensitivity)
RFin
-110
dBm
Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
TDA 5200
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min 4 5 6 7 Output impedance, fRF=869 MHz Voltage Gain Antenna to MI fRF=434 MHz Voltage Gain Antenna to MI fRF=869 MHz Noise Figure S22 LNA GAntMI GAntMI NFLNA Limit Values typ max Unit Test Conditions L Item
42 40 t.b.d.
dB dB
Signal Input LNI, VTHRES = GND, low gain mode
Signal Output LNO, VTHRES = GND, low gain mode
5 6 7
Voltage Gain Antenna to MI fRF=434 MHz Voltage Gain Antenna to MI fRF=869 MHz Noise Figure
GAntMI GAntMI NFLNA
22 19 t.b.d.
dB dB
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 3 50 V A
Signal THRES (PIN 23) 1 Input Voltage range VTHRES 0 VS-1V V see Section 4.1
Wireless Components
5-5
Specification, March 2000
dB
4
Output impedance, fRF=869 MHz
S22 LNA
0.868 / -26.3 deg
3
Output impedance, fRF=434 MHz
S22 LNA
0.897 / -13.6 deg
2
Gain fRF=869 MHz
S21 LNA
0.179 / 109.1deg
1
Gain fRF=434 MHz
S21 LNA
0.183 / 140.6 deg
6
Input 3rd order intercept point fRF=869 MHz
IIP3LNA
-5
dBm
matched input
5
Input 3rd order intercept point fRF=434 MHz
IIP3LNA
-10
dBm
matched input
4
Input level @ 1dB C. P fRF = 869 MHz
P1dBLNA
-6
dBm
matched input
3
Input level @ 1dB C. P fRF = 434 MHz
P1dBLNA
-18
dBm
matched input
2
Input impedance, fRF=869 MHz
S11 LNA
0.738 / -73.5 deg
1
Input impedance, fRF=434 MHz
S11 LNA
0.873 / -34.7 deg
dB
0.866 / -24.2 deg
TDA 5200
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min 2 3 4 LNA low gain mode LNA high gain mode Current in VTHRES VTHRES ITHRES_in 0 2.8 3 5 VS Limit Values typ max V V nA or shorted to Pin 24 Unit Test Conditions L Item
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out ITAGC_in 4.2 1.5 A A RSSI > VTHRES RSSI < VTHRES
MIXER Signal Input MI/MIX (PINS 8/9)
Signal Output IFO (PIN 12) 1 2 3 4 5 Output impedance Conversion Voltage Gain fRF=434 MHz Conversion Voltage Gain fRF=869 MHz Noise Figure, SSB (~DSB NF+3dB) RF to IF isolation ZIFO GMIX GMIX NFMIX ARF-IF 330 +19 +18 t.b.d. t.b.d. dB dB
LIMITER Signal Input LIM/X (PINS 17/18) dB
2 3 4
RSSI dynamic range RSSI linearity Operating frequency (3dB points)
DRRSSI LINRSSI fLIM
60
80
Wireless Components
5-6
Specification, March 2000
5
10.7
23
MHz
1
dB
1
Input Impedance
ZLIM
264
330
396
dB
dB
4
Input 3rd order intercept point fRF=869 MHz
IIP3MIX
-26
dBm
3
Input 3rd order intercept point fRF=434 MHz
IIP3MIX
-28
dBm
2
Input impedance, fRF=869 MHz
S11 MIX
0.918 / -28.1 deg
1
Input impedance, fRF=434 MHz
S11 MIX
0.942 / -14.4 deg
TDA 5200
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min DATA FILTER Limit Values typ max Unit Test Conditions L Item
FILT
2 3
RSSI Level at Data Filter Output SLP RSSI Level at Data Filter Output SLP
RSSIlow RSSIhigh
0.9 2.8
V V
LNA in high gain RFIN=-103dBm LNA in high gain. RFIN=-30dBm
SLICER Signal Output DATA (PIN 25)
SLIC
2 3 4 5
Capacitive loading of output LOW output voltage HIGH output voltage Output current
Cmax
SLIC
20 0 VS-1V 200
pF V V A
VSLIC_L VSLIC_H ISLIC_out
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 3 4 LOW output voltage HIGH output voltage Load current Leakage current VSLIC_L VSLIC_H Iload Ileakage 700 0 VS-1 500 V V A nA
CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 2 3 4 5 Operating frequency Input Impedance @ ~6MHz Input Impedance @ ~13MHz Serial Capacity @ ~6MHz Serial Capacity @ ~13MHz fCRSTL Z1-28 Z1-28 CS 6=C1 CS13=C1 6 -900 +j750 -450 +j1250 8.7 5.3 14 MHz pF pF fundamental mode, series resonance
Wireless Components
5-7
Specification, March 2000
1
Useable bandwith
BWBB
100
kHz

1
Useable bandwidth
BWBB
100
kHz
TDA 5200
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min PLL Signal LF (PIN 15) 1 Tuning voltage relative to Vs VTUNE 0.4 1.6 2.4 V Limit Values typ max Unit Test Conditions L Item
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current PDWN Start-up Time until valid IF signal is detected PWDNO
N
0 2.8 t.b.d.
0.8 VS
V V A
PWDNOff IPDWN TSU
1
ms
VCO MULTIPLEXER Signal FSEL (PIN 11) 1 2 3 fRF range 434 MHz fRF range 869 MHz Input bias current FSEL VFSEL VFSEL IFSEL 1.4 0 200 4 0.2 V V A FSEL tied to GND or open
PLL DIVIDER Signal CSEL (PIN 16) 1 2 3 fCRSTL range 6.xxMHz fCRSTL range 13.xxMHz Input bias current CSEL Measured only in lab. VCSEL VCSEL ICSEL 1.4 0 5 4 0.2 V V A CSEL tied to GND or open
Wireless Components
5-8
Specification, March 2000
TDA 5200
Reference
5.2 Test Circuit
The device performance parameters marked with in Section 5.1.3 were measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDA5100 in an evaluation kit that may be ordered on the INFINEON RKE Webpage www.infineon.com/rke
Infineon Technologies Design Center Graz
TITLE: TDA5200 /-01 /-02 Evaluatio
n Board
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5-9
Specification, March 2000
DATE: Jul.19, 1999
FILE: -10 V 2.0
TDA 5200
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 10
Specification, March 2000
TDA 5200
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 11
Specification, March 2000
TDA 5200
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5200 without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials Ref R1 R2 R3 R4 R5 R6 L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Q2 Value 100k 100k 820k 120k 180k 10k 434 MHz: 15nH 869 MHz: 3.3nH 434 MHz: 8.2pF 869 MHz: 3.9nH 1pF 434 MHz: 4.7pF 869 MHz: 3.9pF 434 MHz: 6.8pF 869 MHz: 5.6pF 100pF 47nF 434 MHz: 10nH 869 MHz: 3.9pF 100pF 434 MHz: 33pF 869 MHz: 22pF 100pF 10nF 10nF 220pF 47nF 470pF 47nF 15pF 8.2pF (fRF - 10.7MHz)/32 or (fRF - 10.7MHz)/64 Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% Toko, PTL2012-F15N0G Toko, PTL2012-F3N3C 0805, COG, 0.1pF Toko, PTL2012-F3N9C 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 5% 1206, X7R, 10% Toko, PTL2012-F10N0G 0805, COG, 0.1pF 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, X7R, 10% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 5% 0805, COG, 1% 0805, COG, 1% HC49/U, fundamental mode, CL = 12pF, e.g. 434.2MHz: Jauch Q 13,23437-S11-1323-12-10/20 e.g. 868.4MHz: Jauch Q 13,40155-S11-1323-12-10/20
Wireless Components
5 - 12
Specification, March 2000
TDA 5200
Reference
Table 5-4 Bill of materials (continued) Ref F1 X2, X3 X1, X4, S1, S5 S4 IC1 TDA 5200 Value SFE10.7MA5-A or SKM107M1-A20-10 142-0701-801 Specification Murata Toko Johnson 2-pole pin connector 3-pole pin connector, or not equipped Infineon
Please note that in case of operation at 434 MHz a capacitor has to be soldered in place of L2 and an inductor in place of C6.
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA52o0 in conjunction with a Microchip HCS515 decoder.
Table 5-5 Bill of Materials Addendum Ref R21 R22 R23 R24 R25 C21 C22 IC2 T1 D1 Value 22k 100k 22k 820k 560k 100nF 100nF HCS515 BC 847B LS T670-JL Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 1206, X7R, 10% 1206, X7R, 10% Microchip Infineon Infineon
Wireless Components
5 - 13
Specification, March 2000
TDA 5200
List of Figures
List of Figures
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-2 3-9 4-2 4-3 4-4 4-5 4-7 4-7 5-9 5-10 5-10 5-11
Wireless Components
List of Figures - 1
Specification, March 2000
TDA 5200
List of Tables
List of Tables
Table 3-1 Table 3-4 Table 4-1 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDWN pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Division Ratio Dependence on States of FSEL and CSEL . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C . . . . . . . . . Operating Range, Ambient temperature TAMB= -40C ... + 85C . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA 25 C, VVCC = 8.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-12 4-6 5-2 5-3 5-4 5-12 5-13
Wireless Components
List of Tables - 1
Specification, March 2000
TDA 5200
List of Tables
Wireless Components
List of Tables - 2
Specification, March 2000

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